An electronic circuit tester (or automated test equipment) is designed to test the performance of a device or an integrated circuit (IC). An electronic circuit tester may be used to test finished packaged devices and integrated circuits at various stages of manufacture of the device or an integrated circuit from the initial substrate processing stage to the final packaging stage.
A conventional programmable electronic circuit tester typically includes a test head that is electrically connected to one or more racks of electronic test and measurement instruments (e.g., AC and DC electrical signal generators, and signal analyzers, such as an oscilloscope and a network analyzer). The test head typically interfaces to a device or an integrated circuit through a load board that, in turn, is connected to a probe card (or fixture board). An electronic circuit tester typically includes a separate test channel for each terminal of a device to be tested. Each test channel is connected to a device testing resource that transmits a test signal to a device terminal and receives and processes one or more output signals appearing at respective terminals of the device. A single device testing resource may be connected to a single test channel in a per pin architecture or it may be connected to multiple test channels in a shared architecture. The load board and probe card assemblies provide signal paths between the circuit boards that are mounted in the test head and the terminals of a device to be tested. In general, the configuration of the load board depends on the category (e.g., analog or digital) of device or integrated circuit being tested. The configuration of the probe card, on the other hand, typically is specific to the family of devices or integrated circuits being tested. The test head may be mounted pivotally on a dolly or other adjustable support mechanism so that the electronic circuit tester may be used to test both packaged devices and integrated circuits.
FIGS. 1 and 2 show an embodiment of an electronic circuit tester 10 (e.g., an ATE system available from Agilent Technologies, Inc. of Palo Alto, Calif., U.S.A.) that includes a test head 12 and a rack 14 of electronic test and measurement instruments, which may include, for example, AC and DC electrical signal generators, and signal analyzers, such as an oscilloscope and a network analyzer. The test head 12 is electrically connected by cables that are routed through a conduit 16 to the rack 14 of electronic test and measurement instruments. A load board 18 provides a set of test connectors for interfacing the test channels within test head 12 with a probe card 20. The test head 12 typically contains a plurality of printed circuit boards that contain electrical circuitry that define test channels for testing a device or an integrated circuit. The load board 18 physically routes electrical test signals from the printed circuit boards in the test head 12 to a physical format that enables direct interfacing to the probe card 20. In some embodiments, load board 18 also may contain test circuitry.
In operation, each circuit board in the test head 12 includes a plurality of device testing resources 21, including pairs of drivers and receivers that define test channels of the electronic circuit tester 10. The drivers transmit output signals to the output test connectors of the load board 18 and the receivers receive input signals from the input test connectors of the load board 18. Typically, there are a plurality of pairs of drivers and receivers on a single circuit board. Each circuit board also may include a parametric measurement unit that is configured to quantify or measure signals and to provide calibration data for the drivers and receivers. Typically, multiple pairs of relays are configured to route signals to respective pairs of drivers and receivers of each circuit board. In operation, one set of relays selectively connects and disconnects the drivers and receivers from the load board test connectors, and another set of relays selectively connects and disconnects the test connectors to, for example, the parametric measurement unit.
In other embodiments, the device testing resources are located on circuit boards mounted inside the rack 14 of electronic test and measurement instruments.
The probe card 20 may connect to load board 18 through a plurality of test connectors (e.g., pogo pins or mating electrical connectors). The probe card 20 has multiple sites for concurrently interfacing with multiple respective test sites on a substrate 22. Each probe card site typically includes a pattern of probe connectors 24 corresponding to the pattern of contacts of a test site on a die of the substrate 22. Probe card 20 contains conductive traces that route electrical test signals from the load board 18 to the probe connectors 24. In some implementations, the probe connectors 24 are probe needles that are precision-manufactured so that they terminate in a common plane.
In operation, test signals are transmitted from the test channels of the test head 12 to drive selected terminals of the integrated circuits on the substrate 22. Response signals are transmitted from selected terminals of the integrated circuits to the corresponding test channels of the test head 12. By controllably varying the output levels of the test signals and monitoring the response signals, the electronic circuit tester 10 may test the functional operation of the integrated circuits on substrate 22 and may verify whether the components of the integrated circuits are operating within specified tolerance values or ranges.
Test head 12 may be mounted pivotally on a dolly 26 or other adjustable support mechanism so that electronic circuit tester 10 may be used to test both packaged devices and integrated circuits. The pivotable connections enable test head 12 to be positioned in an approximately upward facing horizontal position to enable an operator to mount an appropriate load board and probe card to the test head 12. The test head 12 may be pivoted to a downward facing horizontal position to enable the probe card 20 to interface with electrical terminals of the integrated circuits on the substrate through the probe connectors 24.
The operation of the electronic circuit tester 10 typically is controlled by an application program executing on a computer 28. The application program may be implemented by one or more respective software modules. In some implementations, each test channel includes a respective test processor, and the computer 28 downloads application programs to the test processors for execution.
Some electronic circuit testers are designed to test multiple semiconductor devices that are arranged in die regions of semiconductor wafers. These testers typically include in the test head a prober that holds a semiconductor wafer. In operation, the prober moves the wafer so that different test site locations on the wafer are aligned with the probe card. In some designs, the devices are tested one die at a time. Other designs include probe cards that have multiple sites for testing multiple devices on different respective dice at the same time.
Typically, the testing sites on the probe card are arranged in a rectangular array and the number of probe card sites equals the number of device testing resources in the electronic circuit tester. The test site locations on semiconductor wafers, however, typically are arranged in non-rectangular arrays. Therefore, during some touchdowns of the probe card onto the test site locations, some of the probe card sites do not contact test site locations, reducing the utilization of the device testing resources.
For example, FIG. 3A shows an exemplary array of test site locations 30 on a substrate 32. Each test site location 30 typically corresponds to a die on the substrate 32 and includes a plurality of contacts that allow at least one integrated circuit in the die to be tested. FIG. 3B shows a probe card 34 superimposed on the substrate 32 at four different touchdown positions, which are labeled A, B, C, and D. The probe card 34 includes a square array of four testing sites that are arranged to coincide with the test site locations 30. In the illustrated example, the load board 18 (FIG. 2) connects each testing site of the probe card 32 to a respective device testing resource of the electronic circuit tester 10 with a fixed (i.e., non-configurable) electrical connection. Due to the mismatch between the non-rectangular array of test site locations 30 and the square array of testing sites on the probe card 34, one probe card testing site (highlighted dark gray in FIG. 3B) in each touchdown position is not aligned with a corresponding test site location 30. As a result, only 75% of the device testing resources are used during each touchdown. Thus, the fixed resource allocation provided by this example achieves a resource utilization of only 75%.
Configurable probe cards have been proposed to address this problem and thereby increase resource utilization. These configurable probe cards contain probe wires or other contact mechanisms for more test sites than the number of available device testing resources. These probe cards typically include a switch array that is placed between the device testing resources and the probe wires to change which of the sites on the probe card are connected to the device testing resources. For example, FIG. 4 shows a multiplex matrix 40 that includes n×m switches 42 that allow m resources to connect to n probe card sites, where m and n are integers. In this example, m sets of n switches enable each resource to be connected to each of the n probe card sites. The multiplex matrix 40 allows the m resources to be allocated to different sets of m probe card sites for different touchdowns in a way that increases the utilization of the device testing resources. For example, with respect to the exemplary probe card 34 shown in FIG. 3B, a three-by-four multiplex matrix could be used to allocate three device testing resources to the three active probe card sites in each of the four touchdowns A, B, C, D. In this case, the utilization of the three resources would be 100%.
In some implementations of the configurable probe cards that have been proposed, some of the device testing resources may be connected directly to probe card sites. However, a large number of switches are required to connect the device testing resources to the probe card sites with the switching flexibility needed to achieve high resource utilization. The large number of required switches makes these approaches costly and limits the frequencies at which the devices can be tested due to the high site loads. In addition, the physical wiring requirements of these approaches limit the size of the probe card, thereby increasing the number of touchdowns required to test the devices on a wafer.